1. Field of the Invention
This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for forming contact plugs filled in contact holes formed in an insulation film for connection between interconnection layers.
2. Description of the Related Art
As semiconductor devices such as ICs and LSIs are more miniaturized, the tendency of the interconnection layer structure to be made in a multi-layered form becomes more significant. In the multi-level interconnection, several techniques for connecting the interconnection layers to each other are realized. As one of the techniques, a technique for forming a contact hole in an inter-level insulation film formed between the interconnection layers and filling an electrically conductive material called a plug (contact plug) of tungsten, for example, in the contact holes by the CVD (Chemical Vapor Deposition) method to electrically connect the interconnection layers to each other is known in the art. A method for growing the electrically conductive material only in the contact hole (which is hereinafter referred to as selective CVD) has an advantage that a metal film acting as an interconnection layer can be planarize since the plug is filled in the contact hole and therefore the method is often used. The above-described technique for filling the contact plug in the contact hole to connect the interconnection layers to each other is disclosed in NIHON KINZOKU GAKKAI (Institute of Metal of Japan) Proceeding Paper, vol. 28, No. 1 (1989), pp. 48 to 54, for example.
When a plug is filled into a contact hole formed in the inter-level insulation film to connect the first-level interconnection layer and second-level interconnection layer formed on the semiconductor substrate to each other, it is necessary to eliminate a natural oxidation film formed on that portion of the first-level interconnection layer which is exposed in the contact hole as the preprocessing. Therefore, for example, after the natural oxidation film is eliminated by effecting the plasma etching by use of a gas containing halogen such as BCl.sub.3, a plug of tungsten (W) or the like is filled only in the contact hole without depositing the plug material on the inter-level insulation film.
However, with the above method, if the temperature of the semiconductor substrate is high or something which acts as a core for deposition of the plug material of tungsten or the like lies on the surface of the inter-level insulation film at the time of selective growth, the plug material will be deposited not only in the contact hole but also on the inter-level insulation film. For example, when WF.sub.6 is reduced by SiH.sub.4, tungsten is deposited on the interconnection material in the contact hole, and at the same time, tungsten grows from the above core and deposited on the inter-level insulation film around the contact hole.
The interconnection structure in the conventional semiconductor device is explained in detail with reference to FIG. 1. For example, a P-type silicon substrate is used as a semiconductor substrate 1 and a field oxide film 2 is formed as an element isolation region on the surface of the semiconductor substrate 1. For example, an N well region 3 is formed in that portion of the semiconductor substrate 1 which lies in the element region and P-type source and drain regions 4-1, 4-2 which act as active regions of a transistor are formed in the N well region 3. A gate oxide film 5 is formed on the channel region between the source and drain regions 4-1 and 4-2 and a polysilicon gate 6 is formed on the gate oxide film 5. On the resultant structure, a first-level inter-level insulation film 20 which is formed of a BPSG (boro-phospho silicate glass) film, TEOS (tetraethyl orthosilicate) film formed by heat decomposition of organic oxirane or the like and whose surface is planarize by the heat treatment is formed. A first-level metal interconnection layer 21 formed of Al is formed on the inter-level insulation film 20. The metal interconnection layer 21 and inter-level insulation film 20 are covered with a second-level insulation insulation film 22 of BPSG or the like. The surface of the inter-level insulation film 22 is planarize by the heat treatment and a second-level metal interconnection layer 23 formed of Al or the like is formed thereon. The metal interconnection layer 23 is covered with and protected by a protection insulation film 24.
The polysilicon gate 6 and the first-level metal interconnection layer 21 are electrically connected to each other via a contact plug 25-1 formed of tungsten or the like and filled in a contact hole formed in the inter-level insulation film 20. Likewise, The first-level metal interconnection layer 21 and the second-level metal interconnection layer 23 are electrically connected to each other via a contact plug 25-2 formed of tungsten or the like and filled in a contact hole formed in the inter-level insulation film 22. The contact plugs 25-1 and 25-2 are formed by the selective CVD method as described before.
Next, a filling process of the contact plug 25-2 is explained with reference to FIGS. 2A to 2D. FIGS. 2A to 2D are cross sectional views sequentially showing the manufacturing steps of a multi-level interconnection structure section A surrounded by one-dot-dash lines in FIG. 1. First, as shown in FIG. 2A, Al is vapor-deposited on a semiconductor substrate (first-level inter-level insulation film 20) which is not shown in the drawing, and then the Al film is patterned to form the first-level metal interconnection layer 21. Next, the second-level inter-level insulation film 22 is formed to cover the interconnection layer 21. A contact hole 26 is formed in that portion of the inter-level insulation film 22 which lies on the metal interconnection layer 21 by the anisotropic etching method such as RIE so as to expose part of the surface of the metal interconnection layer 21 in the contact hole 26. At this time, a natural oxidation film 27 is formed on the exposed surface of the metal interconnection layer 21.
Next, the natural oxidation film on the first-level metal interconnection layer 21 is removed by the plasma etching using a gas containing halogen such as BCL.sub.3 to obtain the structure shown in FIG. 2B.
After the above process, tungsten is selectively grown on that part of the metal interconnection layer 21 which lies in the contact hole 26 by the reducing reaction of WF.sub.6 so as to fill the contact plug 25-2 in the contact hole 26 (FIG. 2C). The selective CVD is based on the fact that the selectivity is caused by a difference in the material of a portion to be deposited and the reduction speed of halide of tungsten becomes extremely different if the material of the substrate surface is different. Generally, tungsten is deposited on a conductive material, but almost no tungsten is deposited on an insulation material.
Next, Al is vapor-deposited on the inter-level insulation film 22 and the Al film is patterned to form the second-level metal interconnection layer 23. The first-level metal interconnection layer 21 and the second-level metal interconnection layer 23 are electrically connected to each other via the contact plug 25-2. After this, an inter-level insulation film or protection insulation film 24 is formed on the resultant structure to obtain the interconnection structure shown in FIG. 2D.
However, if impurities are present on the surface of the inter-level insulation film 22 or the temperature of the semiconductor substrate is high when the selective CVD for forming the contact plug 25-2 is effected, a core (particle) 28 of tungsten is deposited on the surface of the inter-level insulation film 22 as shown in FIG. 2C. As a result, tungsten grows not only on the metal interconnection layer 21 in the contact hole 26 but also from the core 28, thereby making it impossible to maintain the above-described selectivity. In the CVD method, as the film formation temperature is higher, the growth speed becomes higher and the film quality becomes uniform, and it is advantageous, but if the contact plug is deposited at high temperatures of 200.degree. to 400.degree. C., it is also deposited on the insulation material. On the other hand, if the film formation temperature is lowered, the amount of deposition of the particles becomes less and the selectivity can be enhanced, but the film formation speed becomes low and time for the manufacturing process becomes longer and the film quality becomes non-uniform and contact defects tend to easily occur.